Timer Interrupt Period / Clock Divider Calculator

Interrupt period is determined by Period = (PSC+1)×(ARR+1)÷Clock. Even for the same period, there are many (PSC, ARR) combinations, which affect the readability of count clock (e.g., 1MHz = 1µs steps). This tool's reverse-calculation enumerates divisors of the target ratio Clock÷Frequency to cover all error-free solutions, and presents candidates in order of minimum error → most readable count clock → smallest divisor.

Maximum measurable period = Maximum Prescaler × Maximum Count ÷ Clock. For example, STM32 16-bit timer + 72MHz has a limit of ~59.65 seconds, and SysTick (24-bit, ÷8) + 72MHz has a limit of ~1.86 seconds. Periods exceeding this cannot be created in a single overflow and require software counters or timer chaining. This tool displays the maximum/minimum period above the candidate table.

STM32 divides by (register value + 1) for both prescaler and counter (PSC+1, ARR+1). AVR has discrete prescaler choices {1,8,64,256,1024} and period is TOP+1. SysTick has no prescaler (÷8 is a CLKSOURCE selection) and uses a 24-bit down counter where period is (RELOAD+1)÷Clock. This tool absorbs these differences through preset parameters (offset, width, discrete sets).